More than Moore - the challenges of 3 dimensional IC integration
Frank P. Averdung
Chief Executive Officer
SUSS MicroTec AG
Time: 11:15 – 12:00, Tue, 15 Dec 2009
Room: 301/302
Abstract
The ITRS roadmap for CMOS ICs relies on the shrinking of chip structures which is also the traditional way to lower device costs. R&D expenses to extend the roadmap below 32nm are extraordinarily growing while physical challenges such as electrical, thermal and life time issues will become more severe. Only a limited number of companies and consortia will be able to afford this investment into technology and equipment. In order to continue with a business model that makes sense, many companies will have to turn to other methods to increase circuit density, such as 3-dimensional integration. Chips manufactured in current technology nodes can be stacked on top of each other, so that the number of transistors in the footprint will multiply with the number of chips in a stack. Although this creates a different set of technical challenges, it allows companies to have a significant advantage while boosting product capabilities that are in high demand.
To become successful the 3D packaging technology, especially as a wafer level process, needs the development of dedicated process technologies. Among the key challenges are the formation of "Through Silicon Vias" (TSV) requiring appropriate lithography for TSV etch mask, front to backside registration as well as spray coating for larger sized vias. Temporary bonding allows for mounting of wafers on carriers for subsequent thinning and backside processing. Permanent bonding for die to wafer (D2W) and wafer to wafer (W2W) are the most commonly used methods for 3D stacking and interconnecting with TSV. High precision front to backside alignment and exposure tools are used to create TSV with the via last process.
New approaches are being developed for process monitoring, yield enhancement and WLR testing.
Tools and methodologies for 3D IC testing determine the testability of 3D stacks. Special requirements for 3D testing are high positional accuracy to hit small targets, high z-axis accuracy to minimize surface injury and probe force and the use of vertical probe cards in production as well as in engineering test.
This talk shall give a glance into the future of 3D IC activities and the need for organizations to participate in the R&D efforts to capitalize on the growth opportunities in front of us.
Biography
Frank Averdung graduated from RWTH Aachen with a degree in Electrical Engineering before beginning his professional career in the semiconductors division of Siemens AG in 1985. After various positions in Germany and abroad, the native Rhinelander took worldwide responsibility for the 32-bit microprocessors range as a Product Marketing Manager. In 1990 Averdung changed to National Semiconductor as a Corporate Marketing Manager for two years before moving on to ITT Semiconductor in 1992, first as Marketing Director US & Far East and later as Director of the American subsidiary. Before taking over as the Managing Director of the European ETEC Systems companies in 1999, Frank Averdung worked as a General Manager at Applied Materials in Munich for three years. From 2003 to 2006, as CEO of NaWoTec GmbH, Mr. Averdung substantially contributed to the successful development of the mask equipment business for the semiconductor industry and the later integration of the company into Carl Zeiss Semiconductor Metrology Systems (SMS).
Before his appointment to the SUSS MicroTec AG Management Board, Frank Averdung was the Managing Director of Carl Zeiss SMS GmbH, Jena, and President and General Manager of Carl Zeiss SMT Inc., Peabody, Massachusetts, USA.
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