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For more
enquiry,
please contact
ISIC-2009
Conference Manager
Mary Teng
c/o A’Tenga C. E.,
80 Genting Lane, Genting
Block, #10-04, Ruby Industrial Complex,
Singapore 349565.
Tel: +65-90309898,
Fax: +65-68440630,
Email: isic2009@atenga.sg
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Program
Download PDF Version Final Program
Conference-at-a-Glance
Monday, 14 Dec 2009 |
09:00 – 12:15 |
Full Day Tutorial, Morning Part |
12:15 – 14:00 |
Lunch |
14:00 – 17:00 |
Full Day Tutorial, Afternoon Part
|
Tuesday, 15 Dec 2009 |
09:00 – 09:30 |
Opening Ceremony |
09:30 – 10:00 |
Launch of New Integrated Circuit Design Centre of Excellence |
10:00 – 10:30 |
Tea Break |
10:30 – 11:15 |
Keynote 1: Bram Nauta |
11:15 – 12:00 |
Keynote 2: Frank P. Averdung |
12:00 – 13:30 |
Lunch |
13:30 – 15:00 |
Technical Session |
15:00 – 15:30 |
Tea Break |
15:30 – 17:40 |
Technical Session |
19:00 |
Cocktail Reception (Conrad Centennial Hotel, Level 2, North East Ballroom) |
19:30 |
Banquet (Conrad Centennial Hotel, Level 2, North East Ballroom)
|
Wednesday, 16 Dec 2009 |
08:45 – 10:15 |
Technical Session |
10:15 – 10:45 |
Tea Break |
10:45 – 12:15 |
Technical Session |
12:15 – 13:30 |
Lunch |
13:30 – 15:00 |
Technical Session |
15:00 – 15:30 |
Tea Break |
15:30 – 17:20 |
Technical Session |
REGISTRATION
The registration desk is located at the foyer area, outside 311/312 Room, Level 3, Suntec Singapore
International Convention & Exhibition Centre. The opening hours are:
| Monday, 14 Dec |
Tutorial registration |
8.15 am |
| Monday, 14 Dec |
Symposium Registration |
3.00 pm - 5.30pm |
| Tuesday, 15 Dec |
Symposium Registration |
8.00 am |
| Wednesday, 16 Dec |
Symposium Registration |
8.30 am |
Lecture Sessions
Time \ Room |
308 |
309 |
310 |
311 |
312 |
15 Dec
Tuesday
13:30 – 15:00 |
A1
ADC |
B1
Special Session
10 |
C1
Power Management IC |
D1
Digital IC I |
E1
RF IC I |
Page 2 |
Page 2 |
Page 3 |
Page 3 |
Page 4 |
15 Dec
Tuesday
15:30 – 17:40 |
A2
Special Session
9a |
B2
Special Session
9b |
C2
Special Session
3 |
D2
Special Session
8 |
E2
Special Session
11 |
Page 5 |
Page 6 |
Page 7 |
Page 8 |
Page 9 |
16 Dec
Wednesday
8:45 – 10:15 |
A3
Special Session
2 |
B3
Special Session
5 |
C3
Mixed-Signal IC |
D3
Digital IC II |
E3
Semiconductor Devices |
Page 10 |
Page 10 |
Page 11 |
Page 11 |
Page 12 |
16 Dec
Wednesday
10:45 – 12:15 |
A4
Special Session
6 |
B4
Special Session
12 |
C4
Analog IC |
D4
RF IC II |
E4
Computer Aided Design |
Page 12 |
Page 13 |
Page 13 |
Page 14 |
Page 14 |
16 Dec
Wednesday
13:30 – 15:00 |
A5
Amplifier |
B5
System-on-Chip |
C5
Simulation, Verification and Testability |
D5
Current Mode Circuits |
E5
Reliability and Failure Analysis |
Page 15 |
Page 15 |
Page 16 |
Page 16 |
Page 17 |
16 Dec
Wednesday
15:30 – 17:20 |
A6
Special Session
1 |
B6
Special Session
4 |
C6
Special Session
7 |
D6
Special Session
13 |
E6
EMC/EMI |
Page 18 |
Page 19 |
Page 20 |
Page 21 |
Page 21 |
Poster Sessions
Time \ Venue |
Level 3 Foyer |
16 Dec, Wednesday
10:45 – 12:15 |
P1
Device and IC Technology & Design Automation |
Page 22 |
16 Dec, Wednesday
13:30 – 15:00 |
P2
Integrated Circuits & Integrated Systems |
Page 23 |
Tuesday, 15 Dec 2009 |
A1 Integrated Circuits: ADC
Time: Tuesday, 15 Dec 2009, 13:30 – 15:00
Room: 308
Chair: Liter Siek |
13:30
A1-1 Low Power Current Mode Pipelined A/D Converter with 2.5-bit/stage and Digital Correction
Krzysztof Wawryn, Robert Suszynski, Bogdan Strzeszewski, Poland
13:48
A1-2 A High-resolution Time-interleaved Delta-sigma Modulator with Low Oversampling
Chun-Yao Lu, Chang-Yu Hsieh, Hsin-Liang Chen, Jen-Shiun Chiang, Taiwan
14:06
A1-3 Stability Analysis and System Design of Sigma-delta Modulators
Chih-Yuan Chen, Rong-Guey Chang, Shuenn-Yuh Lee, Taiwan
14:24
A1-4 A Low-Power Wide-Range Interface Circuit for Nanowire Sensor Array Based on Resistance-to-Frequency
Conversion Technique
Haiqi Liu, Tee Hui Teo, Y. P. Zhang, Singapore
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Tuesday, 15 Dec 2009 |
B1 Special Session 10: Recent Progress in Structured ASICs
Time: Tuesday, 15 Dec 2009, 13:30 – 15:00
Room: 309
Chair: Rung-Bin Lin |
13:30
B1-1 Via-configurable Logic Block Architectures for Standard Cell like Structured ASICs
Hui-Hsiang Tung, Yu-Chen Chen, Da-Wei Hsu, Shih-Jung Hsu, Sin-Yu Chen, Rung-Bin Lin, Taiwan
(Invited Paper)
13:48
B1-2 Via-programmable Logic Array VPEX2 with Configurable DFF using 2 Logic Elements
Takeshi Fujino, Tomohiro Nishimoto, Yuichi Kokusyo, Masaya Yoshikawa, Guy Lemieux, Japan
14:06
B1-3 Using Structured ASIC to Improve Design Productivity
Yu-Wen Tsai, Kun-Chen Wu, Hui-Hsiang Tung, Rung-Bin Lin, Taiwan
14:24
B1-4 DFM-aware Structured ASIC Design
Salman Gopalani, Rajesh Garg, Sunil P. Khatri, Mosong Cheng, USA
14:42
B1-5 A PTL based Highly Testable Structured ASIC Design Approach
Kanupriya Gulati, Nikhil Jayakumar, Sunil P. Khatri, USA
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Tuesday, 15 Dec 2009 |
C1 Integrated Circuits: Power Management IC
Time: Tuesday, 15 Dec 2009, 13:30 – 15:00
Room: 310
Chair: Wing Hung Ki and Meng Tong Tan |
13:30
C1-1 A Low Dropout Regulator for SoC with High Power Supply Rejection and Low Quiescent Current
Chenchang Zhan, Wing-Hung Ki, Hong Kong, China
13:48
C1-2 A Low Dropout Linear Regulator with High Power Supply Rejection
Huei-Sheng Jhuang, Jia-Hui Wang, Zi-Yu Zeng, Chien-Hung Tsai, Taiwan
14:06
C1-3 A Nonlinear Control Buck Converter with Fast Transient Response
Sizhen Li, Xuecheng Zou, Xiaofei Chen, China
14:24
C1-4 Li-ion Battery Charger with Smooth-switch-over Four-stage Control
Yueming Sun, Xiaobo Wu, Menglian Zhao, China
14:42
C1-5 High Efficiency High Integration Green Converter
Jiana Lou, Xiaobo Wu, China
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Tuesday, 15 Dec 2009 |
D1 Integrated Circuits: Digital IC I
Time: Tuesday, 15 Dec 2009, 13:30 – 15:00
Room: 311
Chair: Wang Ling Goh |
13:30
D1-1 A Lightweight Memory Encryption Cache Design and Implementation for Embedded Processor
Zhenglin Liu, Wenjie Huo, Xuecheng Zou, Yingyan Lin, China
13:48
D1-2 A 1.8 V to 3.3 V Level-converting Flip-flop Design for Multiple Power Supply Systems
Chua-Chin Wang, Jen-Wei Liu, Ron-Chi Kuo, Shu-Min Li, Sying-Jyan Wang, Taiwan
14:06
D1-3 A Robust, Low-complexity & Ultra-low Power Manchester Decoder for Wireless Sensor Nodes
Chin Yann Pang, Pradeep Kumar Gopalakrishan, Tee Hui Teo, Singapore
14:24
D1-4 An Enhanced Low-power High-speed Adder For Error-tolerant Application
Ning Zhu, Wang Ling Goh, Kiat Seng Yeo, Singapore
14:42
D1-5 A New Flip-flop based on Multiple Leakage Reduction Techniques
Weiqiang Zhang, Linfeng Li, Jianping Hu, China
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Tuesday, 15 Dec 2009 |
E1 Integrated Circuits: RF IC I
Time: Tuesday, 15 Dec 2009, 13:30 – 15:00
Room: 312
Chair: Lin Jia |
13:30
E1-1 A Fully Integrated Differential Impulse Radio Transmitter
Jin He, Yue Ping Zhang, Singapore
13:48
E1-2 Low Power Fully Differential Front End for Wireless Sensor Network Application
Lin Jia, Henry Kok Fong Ong, Ben Yeung Bun Choi, Singapore
14:06
E1-3 A 0.18 um CMOS Multi-Gb/s 10-PAM Transmitter
Jikyung Jeong, JeongJun Lee, Jinwook Burm, Korea
14:24
E1-4 A Multi Gbps 10-PAM Receiver in 0.18um CMOS Technology
JeongJun Lee, Jikyung Jeong, Jinwook Burm, Korea
14:42
E1-5 A Fully-integrated Low Power PAM/PPM Multi-channel UWB Transmitter
Caixia Chen, Manh Anh Do, Kiat Seng Yeo, Chirn Chye Boon, Singapore
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Tuesday, 15 Dec 2009 |
A2 Special Session 9a: Munich-Singapore Cooperative Research on Circuits and Systems
Time: Tuesday, 15 Dec 2009, 15:30 – 17:40
Room: 308
Chair: Ulf Schlichtmann and Liter Siek |
15:30
A2-1 Characterization and Implementation of Nonlinear Logic Cell Models for Analog Circuit Simulation
Christoph Knoth, Veit B. Kleeberger, Petra Nordholz, Ulf Schlichtmann, Germany (Invited Paper)
15:48
A2-2 K-locked-loop and its Application in Time Mode ADC
Hon Cheong Hor, Liter Siek, Singapore
16:06
A2-3 Saving Potentials of Adiabatic Logic on System Level: A CORDIC-based Adiabatic DCT
Philip Teichmann, Marius Vollmer, Jurgen Fischer, Benjamin Heyne, Jurgen Gotze, Doris Schmitt-Landsiedel,
Germany
16:24
A2-4 A Circuit-based Behavioral Modeling of Continuous-time Sigma Delta Modulators
Yoon Hwee Leow, Fan Zhang, Li Lian Teh, Liter Siek, Singapore
16:42
A2-5 RaGAzi: A Random and Gradient-based Approach to Analog Sizing for Mixed Discrete and Continuous
Parameters
Michael Pehl, Helmut Graeb, Germany
17:00
A2-6 Tradeoff of Energy and Hardware Resources in High Level Synthesis
Xianwu Xing, Ching Chuen Jong, Singapore
17:18
A2-7 Analog Circuits for Physical Cryptography
Qingqing Chen, Gyorgy Csaba, Xueming Ju, Srinivas Bangalore Natarajan, Paolo Lugli, Ulf Schlichtmann,
Ulrich Ruhrmair, Germany
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Tuesday, 15 Dec 2009 |
B2 Special Session 9b: Munich-Singapore Cooperative Research on Device and Process Technology
Time: Tuesday, 15 Dec 2009, 15:30 – 17:40
Room: 309
Chair: Cher Ming Tan and Paolo Lugli |
15:30
B2-1 Circuit and System Implementations of Molecular Devices
Paolo Lugli, A. Abdellah, E. Albert, Gyorgy Csaba, C. Erlen, B. Fabel, Mary Chan-Park, et. AL, Germany
15:48
B2-2 Transient Electrical Thermal Analysis of ESD Process using 3-D Finite Element Method
Yuejin Hou, Cher Ming Tan, Singapore
16:06
B2-3 Subcircuit Approach to Inventive Compact Modeling for CMOS Varibility and Reliability
X. Zhou, G. J. Zhu, S. H. Lin, Z. H. Chen, M. K. Srikanth, Y. F. Yan, R. Selvakumar, et. AL, Singapore
16:24
B2-4 MOSFET-controlled Emission from Nanoscale Silicon Field Emitters
Thomas Maul, Markus Becherer, Josef Biba, Walter Hansch, Germany
16:42
B2-5 Excimer Laser-Annealed Dopant Segregated Schottky (ELA-DSS) Si Nanowire Gate-All-Around (GAA) pFET
Yoke King Chin, Kin Leong Pey, Navab Singh, Wei Jie Lu, Guo Qiang Lo, Xin Cai Wang, Hong Yu Zheng, Lap
Chan, Singapore
17:00
B2-6 High Performance HfOx ¨CBased Resistive RAM Devices and Its Temperature Dependent Switching
Zheng Fang, Hong Yu, Xiang Li, Kin Leong Pey, Wenjun Liu, Singapore
17:18
B2-7 Towards the optimization of organic solar cells via controlled morphologies
Y. Wang, Xiaowei Sun, Giuseppe Scarpa, Paolo Lugli, Singaporeand Germany
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Tuesday, 15 Dec 2009 |
C2 Special Session 3: Circuits and System Architectures for Advanced Channel Coding and Image Processing Applications
Time: Tuesday, 15 Dec 2009, 15:30 – 17:40
Room: 310
Chairs: Sau-Gee Chen and Pramod Kumar Meher |
15:30
C2-1 A High-performance Multibit-flipping Algorithm for LDPC Decoding
Jui-Hui Hung, Sau-Gee Chen, Taiwan (Invited Paper)
15:48
C2-2 Digital Pixel Sensor with On-line Spatial and Temporal Compression Scheme
Milin Zhang, Amine Bermak, HongKong
16:06
C2-3 Bit-serial Systolic Architecture for 2-D Non-separable Discrete Wavelet Transform
Basant Kumar Mohanty, Pramod Kumar Meher, India
16:24
C2-4 Does the Scanning Pattern Affect Adaptive Quantization Processing?
Milin Zhang, Amine Bermak, HongKong
16:42
C2-5 Accelerating CORDIC for Hough Transform
Sathyanarayana Suchitra, Ravi Kumar Satzoda, Thambipillai Srikanthan, Singapore
17:00
C2-6 A Long Block Length BCH Decoder for DVB-S2 Application
Yi-Min Lin, Jau-Yet Wu, Chien-Ching Lin, Hsie-Chia Chang, Taiwan
17:18
C2-7 Interpolation-based Hard-decision Reed-solomon Decoders
Xinmiao Zhang, Jiangli Zhu, USA
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Tuesday, 15 Dec 2009 |
D2 Special Session 8: Biomedical Electronics and Systems for Patient Diagnosis
Time: Tuesday, 15 Dec 2009, 15:30 – 17:40
Room: 311
Chair: Ronny Veljanovski |
15:30
D2-1 A CMOS Analog Integrated Circuit for Pixel X-ray Detector
David Fitrio, Suhardi Tjoa, Anand Mohan, Ronny Veljanovski, Andrew Berry, Australia (Invited Paper)
15:48
D2-2 Recent Advances in Biomedical Imaging Systems
Andrew Berry, Goran Panjkovic. Stewart Midgley, John Gillam, Chris Hall, Robert Lewis, Australia
16:06
D2-3 Testing of Pixellated CZT and CdTe Detectors at the 200ìm Level
George Jung, Andrew Berry, Stewart Midgley, Goran Panjkovic, Australia
16:24
D2-4 Signal Characteristics and Signal Processing in Read-out Electronics for Radiation Detectors
Goran Panjkovic, David Fitrio, Stewart Midgley, Andrew Berry, Anand Mohan, Australia
16:42
D2-5 Signal Processing and Data Acquisition for Hybrid Pixel Detectors
Adam Lynch, Suhardi Tjoa, Andrew Berry, Australia
17:00
D2-6 Key Challenges for ASIC Design and Implementation for Biomedical Imaging
Goran Panjkovic, David Fitrio, Anand Mohan, Ronny Veljanovski, Suhardi Tjoa, Andrew Berry, Australia
17:18
D2-7 Implementation of a Ratiometric Algorithm to Compute Partial Pressure of Oxygen for a Blood Oxygen
Analyser
Nikhil Joglekar, Ronny Veljanovski, Aladin Zayegh, Australia
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Tuesday, 15 Dec 2009 |
E2 Special Session 11: Low-cost/Low-power Integrated Circuits Design for High Performance Communication
Systems
Time: Tuesday, 15 Dec 2009, 15:30 – 17:40
Room: 312
Chairs: Zhenghao Lu and Jianjun Zhou |
15:30
E2-1 Modeling of A 14-bit, 100-MS/s Pipelined ADC with Digital Nonlinearity Calibration
Xuan Wang, Junxiao Chen, Lenian He, China (Invited Paper)
15:48
E2-2 An ASIC for Data over SONET/SDH Mapping and Path Protection Switching
Lijun Zhang, Aiming Ji, Min Luo, Taiwan
16:06
E2-3 Optimization of Sample/Hold Circuit for High-Speed and High-Resolution ADCs
Junxiao Chen, Lu Zhang, Lenian He, China
16:24
E2-4 Optimized System Design for Fully Integrated Fractional-N PLL
Yunchun Zhu, Jing Jin, Xiaopeng Yu, Jianjun Zhou, China
16:42
E2-5 Design of a Under Voltage Lock Out Circuit with Bandgap Structure
Fuhua Li, Wei Wang, Qiuping Huang, Weiguo Xie, Zhenghao Lu, Taiwan
17:00
E2-6 Design of an Off-line AC/DC Controller based on Skip Cycle Modulation
Fuhua Li, Hanxiang Wang, Zhenghao Lu, Weiguo Xie, Taiwan
17:18
E2-7 An Inductor-less Broadband Design Technique for Transimpedance Amplifiers
Zhenghao Lu, Dandan Chen, Kiat Seng Yeo, Taiwan
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Wednesday, 16 Dec 2009 |
A3 Special Session 2: Modeling and Analysis of Carbon Nanotubes for VLSI Interconnection and Application
in Solar Cell Design
Time: Wednesday, 16 Dec 2009, 08:45 – 10:15
Room: 308
Chair: Masud H. Chowdhury |
08:45
A3-1 Impact of CNT Arrangement on Capacitance and Inductance in Mixed Bundles
Suraj Subash, Sajjad Rahaman, Masud H. Chowdhury., USA (Invited Paper)
09:03
A3-2 High Efficiency Carbon Nanotube Based Solar Cells for Electronics Devices
Suraj Subash, Masud H. Chowdhury, USA
09:21
A3-3 Low-power and Robust Six-FinFET Memory Cell Using Selective Gate-drain/Source Overlap Engineering
Sherif A. Tawfik, Volkan Kursun, USA
09:39
A3-4 Exploiting SWCNT Structural Variability towards the Development of a Photovoltaic Device
Karim EL Shabrawy, Koushik Maharatna, Bashir Al-Hashimi, United Kingdom
09:57
A3-5 Effect of Variability in SWCNT-based Logic Gates
Hamed Shahidipour, Arash Ahmadi, Koushik Maharatna, United Kingdom
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Wednesday, 16 Dec 2009 |
B3 Special Session 5: Ab-initio Modelling of Microacoustic, Microelectronic and Quantum Devices
Time: Wednesday, 16 Dec 2009, 08:45 – 10:15
Room: 309
Chair: Alireza R. Baghai-Wadji |
08:45
B3-1 Computational Analysis of Micro-acoustic Structures using the Finite Element Method
Glenn Matthews, Alireza Baghai-Wadji, Australia (Invited Paper)
09:03
B3-2 On the Construction of Problem-specific Basis Functions for Modelling the Massloading Effects in Micro-acoustic Devices
Hardik Vagh, Alireza Baghai-Wadji, Australia
09:21
B3-3 On the Nature of Eigenpairs Associated with Wave Propagation Problems in Photonic Structures
Alireza Baghai-Wadji, Australia
09:39
B3-4 Zooming into the Near Field: Shear-horizontal Polarized Acoustic Waves
Alireza Baghai-Wadji, Australia
09:57
B3-5 The Construction of Basis Functions for Modelling Closed- and Open Quantum Wire Problems
Andrew J. Simth, Alireza Baghai-Wadji, Australia
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Wednesday, 16 Dec 2009 |
C3 Integrated Circuits: Mixed-Signal IC
Time: Wednesday, 16 Dec 2009, 08:45 – 10:15
Room: 310
Chair: Pak Kwong Chan and Wing Hung Ki |
08:45
C3-1 High-accuracy and Power-efficient Switched-current Memory Cell
Xian Tang, Kong-pang Pun, Ho, Hong Kong
09:03
C3-2 High-speed, Low Switching Noise and Load Adaptive Output Buffer
Ying-Yan Lin, Wen-Jing Kang, Zhao-Xiao Zheng, Wen-Jie Huo, Xue-Cheng Zou, Hong Kong
09:21
C3-3 A 20MHz Switched-current Sample-and-hold Circuit for Current Mode Analog Iterative Decoders
Ming-Yam Lo, Wing-Hung Ki, Wai-Ho Mow, Hong Kong
09:39
C3-4 A Novel 1.2 Gbps LVDS Receiver for Multi-channel Applications
Ying-Yan Lin, Wen-Jing Kang, Jing Zhang, Xiao-Fei Chen, Xue-Cheng Zou, China
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Wednesday, 16 Dec 2009 |
D3 Integrated Circuits: Digital IC II
Time: Wednesday, 16 Dec 2009, 08:45 – 10:15
Room: 311
Chair: Shoushun Chen |
08:45
D3-1 Design and Performance Evaluations of a Silent Data-line SRAM Sense Amplifier
Haitao Fu, Kiat Seng Yeo, Zhi-Hui Kong, Anh Tuan Do, Singapore
09:03
D3-2 A Low-complexity Power-efficient Synchronization Scheme for Wireless Communication System
Bin Zhao, YiSheng Wang, Xin Liu, Yuanjin Zheng, Singapore
09:39
D3-3 Novel Security Strategies for SRAM in Powered-off State to Resist Physical Attack
Wenjing Kang, Kai Yu, Guoyi Yu, Xuecheng Zou, China
09:57
D3-4 Tree Multipliers with Modified Booth Algorithm based on Adiabatic CPL
Binbin Liu, Jianping Hu, China
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Wednesday, 16 Dec 2009 |
E3 Device and IC Technology: Semiconductor Devices
Time: Wednesday, 16 Dec 2009, 08:45 – 10:15
Room: 312
Chair: Chirn Chye Boon |
08:45
E3-1 Analytical High Frequency Channel Thermal Noise Modeling in Deep Sub-micron MOSFETs
Shih Ni Ong, Kiat Seng Yeo, Kok Wai Chew, Lye Hock Chan, Xi Sung Loo, Manh Anh Do, Chirn Chye Boon,
Singapore
09:03
E3-2 High Frequency Drain Current Noise Modeling in MOSFETs under Sub-threshold Condition
Lye Hock Chan, Kiat Seng Yeo, Kok Wai Chew, Shih Ni Ong, Xi Sung Loo, Chirn Chye Boon, Manh Anh Do,
Singapore
09:21
E3-3 Study of a Single Coaxial Silicon Nanowire for On-chip Integrated Photovoltaic Application
Oka Kurniawan, Er-Ping Li, Singapore
09:39
E3-4 Formation of N+/P Junction in GaAs using Pulsed Laser Anneal
Chio Yin Ong, Kin Leong Pey, Xin Cai Wang, Hong Yu Zheng, Choun Pei Wong, Zexiang Shen, Chee Mang Ng,
Lap Chan, Singapore
09:57
E3-5 Alcohol Sensor based on Multi-wall Carbon Nanotube
Chalin Sutthinet, Assuchol Sangnual, Toempong Phetchakul, Thailand
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Wednesday, 16 Dec 2009 |
A4 Special Session 6: Implementation of Low Power and High Flexibility Multimedia Codecs
Time: Wednesday, 16 Dec 2009, 10:45 - 12:15
Room: 308
Chair: Myung Hoon Sunwoo |
10:45
A4-1 Novel Intra Prediction Algorithm using Residual Prediction for Low Power Multimedia Codecs
Sung Dae Kim, Jin Soo Kim, Myung Hoon Sunwoo, Korea (Invited Paper)
11:03
A4-2 VLSI Design to Unify IDCT and IQ Circuit for Multi-standard Video Decoder
Hoyoung Chang, Soojin Kim, Seonyoung Lee, Kyeongsoon Cho, Korea
11:21
A4-3 Impact of Process Variation on Timing Characteristics of MTCMOS Flip-flops for Low-power Mobile
Multimedia Applications
Eun Ju Hwang, Wook Kim, Young Hwan Kim, Korea
11:39
A4-4 Fast H.264/AVC Motion Estimation Algorithm using Adaptive Search Range
Junwoo Lee, Minsu Choi, Youngmin Cho, Jinsang Kim, Won-Kyung Cho, Korea
11:57
A4-5 Dynamic Range Compression Algorithm for Mobile Display Devices using Average Luminance Values
Sungmok Lee, Hagyong Han, Boodong Kwak, Wontae Choi, Bongsoon Kang, Korea
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Wednesday, 16 Dec 2009 |
B4 Special Session 12: Low Computational Complexity Digital Filter Design
Time: Wednesday, 16 Dec 2009, 10:45 - 12:15
Room: 309
Chair: Ya Jun Yu |
10:45
B4-1 An Improved Approach for the Synthesis of Multiplication-Free Highly-Selective FIR Half-Band Decimators
and Interpolators
Tapio Saramaki, Juha Yli-kaakinen, Finland (Invited Paper)
11:03
B4-2 Fast Filter Bank using Mixed-radix Decompositions for an Arbitrary Number of Output Channels
Jun Wei Lee, Yong Ching Lim, Singapore
11:21
B4-3 An Improved Structure and Design Procedure for Signed Power-of-two Lattice QMF Bank
Sang Yoon Park, Ya Jun Yu, Singapore
11:39
B4-4 Antenna Array Synthesis in Presence of Mutual Coupling Effect for Low Cost Implementation
Ling Cen, Zhu Liang Yu, Wee Ser, Singapore
11:57
B4-5 Efficient Multiplierless Designs for 1-D DWT using 9/7 Filters based on Distributed Arithmetic
Basant Kumar Mohanty, Pramod Kumar Meher, India
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Wednesday, 16 Dec 2009 |
C4 Integrated Circuits: Analog IC
Time: Wednesday, 16 Dec 2009, 10:45 - 12:15
Room: 310
Chair: Yuanjin Zheng and Minkyu Je |
10:45
C4-1 A Low-voltage Low-power High Precision Digitally Tunable Transconductance Rectifier
Dong Han, Yuanjin Zheng, Singapore
11:03
C4-2 A Compact Low-offset Voltage and Low Power Rail-to-rail Output Buffer for TFT-LCD Panel
Chuen-Chi Yeh, Jia-Hui Wang, Chien-Hung Tsai, Chin-Tien Chang, Chen-Yu Wang, Taiwan
11:21
C4-3 Nanowire Transistors Applications in Folded-cascode Amplifier Circuits
Shuqin Ye, Juanda Chang, Olivier D. Bernal, Minkyu Je, Singapore
11:39
C4-4 High-input and Low-output Impedance Voltage-mode All-pass Networks
Montree Kumngern, Thailand
11:57
C4-5 Current-controlled Quadrature Oscillator using Only CCCDBAs
Winyu Sonjoi, Worapong Tangsrirat, Wanlop Surakampontorn, Thailand
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Wednesday, 16 Dec 2009 |
D4 Integrated Circuits: RF IC II
Time: Wednesday, 16 Dec 2009, 10:45 - 12:15
Room: 311
Chair: Manh Anh Do |
10:45
D4-1 Zero Power Bypass Variable Gain Splitter for TV Tuner
Frederic Villain, Guillaume Lebailly, France
11:03
D4-2 A Single Ended Input Wideband Variable Gain Low Noise Amplifier with Balanced Differential Output and
Digital AGC for CMMB TV Tuner
Hao Hu, Taotao Yan, Cui Mao, Jianjun Zhou, China
11:21
D4-3 Frequency Resolution Enhancement for Digitally Controlled Oscillators using Series Switched Varactor
Xuan Dai, Weicheng Zhang, Jing Jin, Jianjun Zhou, China
11:39
D4-4 The Novel High Efficiency on Chip Transformers for the CMOS Power Amplifier
Ki-Jin Kim, Tae Ho Lim, K.H. Ahn, Korea
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Wednesday, 16 Dec 2009 |
E4 Design Automation: Computer Aided Design
Time: Wednesday, 16 Dec 2009, 10:45 - 12:15
Room: 312
Chair: Yu Hao and Yvonne Ying Hung Lam |
10:45
E4-1 Heuristic Techniques for Automatic Synthesis of Clock Mesh
Weijian Huang, Guoyong Shi, China
11:03
E4-2 Evaluation of the State-of-the Art Statistical Leakage Estimation Methods using the BSIM4 Transistor Model
Jinwook Kim, Wook Kim, Young Hwan Kim, Korea
11:21
E4-3 DEV: Design Explorer for Verification
John Kah Soon Lau, Ching Ling Low, Malaysia
11:39
E4-4 ILP-based Optimal Multi-threshold Voltages Assignment under Performance Constraints
Chun-Hua Chung, Hsi-An Chien, Hsin-Hsiung Huang, Tsai-Ming Hsieh, Taiwan
11:57
E4-5 High-level Statistical Timing Analysis under Process Variation
Taehoon Kim, Wook Kim, Jinwook Kim, Young Hwan Kim, Korea
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Wednesday, 16 Dec 2009 |
A5 Integrated Circuits: Amplifier
Time: Wednesday, 16 Dec 2009, 13:30 – 15:00
Room: 308
Chair: Pak Kwong Chan and Yuanjin Zheng |
13:30
A5-1 A CMOS Low-power Variable-gain Amplifier with RSSI for a Noncoherent Low Data Rate IR-UWB Receiver
Zhiming Chen, Yuanjin Zheng, Singapore
13:48
A5-2 Feedforward Technique for Offset Cancellation in Broadband Differential Amplifiers
Duy Dong Pham, James brinkhoff,, Kai Kang, Fujiang Lin, Singapore
14:06
A5-3 An Ultra Low-power CMOS EMG Amplifier with High Efficiency in Operation Frequency per Power
Limi Jaya Gibran, Pak Kwong Chan, Singapore
14:24
A5-4 A 3-47dB Gain, +20dBm IIP3, 400MHz VGA for a Pulse-based UWB in 0.18um CMOS
Yen Ju The, Annamalai Arasu Muthukumaraswamy, Singapore
14:42
A5-5 An Offset Cancellation CMOS VGA for GPS Receiver
Tianwang Li, Jinguang Jiang, Bo Ye, China
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Wednesday, 16 Dec 2009 |
B5 Integrated Systems: System-on-Chip
Time: Wednesday, 16 Dec 2009, 13:30 – 15:00
Room: 309
Chair: Shoushun Chen |
13:30
B5-1 Physical Design Challenges for the Jasper Forest SoC
Yuyun Liao, Nishi Raman, Murlikishnan Parameswaran, Mandar Bapat, Phong Bach, Sidharth Murthy, John
Blackburn, USA
13:48
B5-2 A VLSI Architecture for VGA 30 fps Video Segmentation with Affine Motion Model Estimation
Masayuki Miyama, Yoshiki Yunbe, Kouji Togo, Yoshio Matsuda, Japan
14:06
B5-3 A High Normalized Throughput SoC-based Inverse Integer Transform Design for H.264/AVC
Trang T.T. Do, Thinh M. Le, Singapore
14:24
B5-4 Modelling and Estimating the Energy Consumption of Embedded Applications and Operating Systems
Saadia Dhouib, Eric Senn, Jean-Philippe Diguet, Sebastien Le-Fur, Johann Laurent, France
14:42
B5-5 Low Power Pipelined MIPS Processor Design
Karthi Balasubramanian, P. Gautham, R. Parthasarathy, India
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Wednesday, 16 Dec 2009 |
C5 Design Automation: Simulation, Verification and Testability
Time: Wednesday, 16 Dec 2009, 13:30 – 15:00
Room: 310
Chair: Yvonne Ying Hung Lam and Yu Hao |
13:30
C5-1 Local Mismatch in 45nm Digital Clock Networks
Tarun Chawla, Sebastien Marchal, Amara Amara, Andrei Vladimirescu, France
13:48
C5-2 Symbolic Techniques for Statistical Timing Analysis of RCL Mesh Networks with Resistor Loops
Zhigang Hao, Guoyong Shi, China
14:06
C5-3 An Automatic Test Approach for Field Programmable Gate Array (FPGA)
A. W. Ruan, Y. B. Liao, P. Li, W. Li, W. C. Li, China
14:24
C5-4 Full Coverage Manufacturing Testing for SRAM-based FPGA
Y. B. Liao, P. LI, A. W. Ruan, W. Li, W. C. Li, China
14:42
C5-5 Cost-effective Scenarios of CABAC in H.264/AVC Codec
Shyam P. Krishnamurthy, Thinh M. Le, Boon-Leng Ho, Singapore |
Wednesday, 16 Dec 2009 |
D5 Integrated Circuits: Current Mode Circuits
Time: Wednesday, 16 Dec, 2009, 13:30 – 15:00
Room: 311
Chair: Meng Tong Tan |
13:30
D5-1 CMOS Digitally Controlled Current Follower and its Application
Danucha Prasertsom, Worapong Tangsrirat, Thailand
13:48
D5-2 Insensitive Current-tunable Current-mode Multifunction Filter with Minimum Components using Multi-output
Current Followers
Kritsada Bunruang, Worapong Tangsrirat, Thailand
14:06
D5-3 A Digital Brightness Controlled WLED Driver with I2C-bus Interface
Jingyi Song, Shuxu Guo, Yang Liu, Quan Zhou, Yuchun Chang, China
14:24
D5-4 A Wide-Band Half-Wave Rectifier
Montree Kumngern, Thailand
14:42
D5-5 Dual Magnetodiode
Toempong Phetchakul, Sumet Junkamkaw, Thailand
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Wednesday, 16 Dec 2009 |
E5 Device and IC Technology: Reliability and Failure Analysis
Time: Wednesday, 16 Dec 2009, 13:30 – 15:00
Room: 312
Chair: Cher Ming Tan |
13:30
E5-1 Post Breakdown Reliability Enhancement of ULSI Circuits with Novel Gate Dielectric Stacks
Raghavan Nagarajan, Wu Xing, Xiang Li, Liu Wenhu, Lo Vui Lip, Kin Leong Pey, Singapore
13:48
E5-2 Fluxless Reflow of Eutectic Solder Bump using Formic Acid
Yong-Shan Lin, Chun-Hsing Shih, Wei Chang, Taiwan
14:06
E5-3 Implantation-induced Defects Analysis base on Activation Energy Diagnostics
Weera Pengchan, Toempong Phetchakul, Amporn Poyal, Thailand
14:24
E5-4 Requirement for Accurate Interconnect Temperature Measurement for Electromigration Test
Yuejin Hou, Cher Ming Tan, Singapore
14:42
E5-5 Extraction of Diffusion Length Using Junction-less EBIC
Vincent Keng Sian Ong, Chee Chin Tan, K. Radhakrishnan, Singapore |
Wednesday, 16 Dec 2009 |
A6 Special Session 1: Cross Disciplinary Research in Signal Processing, RF Communication and VLSI
Circuit Issues
Time: Wednesday, 16 Dec 2009, 15:30 – 17:20
Room: 308
Chairs: Masud H. Chowdhury |
15:30
A6-1 Information Theoretic Capacity Analysis of Single-walled Carbon Nanotube Bundle VLSI Interconnects
Sajjad Rahaman, Masud H.Chowdhury, USA (Invited Paper)
15:48
A6-2 Ground Bouncing Noise Aware Sequential MTCMOS Circuits with Data Retention Capability
Hailong Jiao, Volkan Kursun, HongKong
16:06
A6-3 Design of a 21 GHz UWB Differential Low Noise Amplifier using .13ìm CMOS Process
S. M. Shahriar Rashid, Apratim Roy, Sheikh Nijam Ali, A. B. M. H. Rashid, Bangladesh
16:24
A6-4 Biologically Inspired Analogue Signal Processing: Some Results Towards Developing Next Generation
Signal Analyzers
Koushik Maharatna, Arash Ahmadi, Eduardo Magieri, United Kingdom
16:42
A6-5 Hard Multiple Generator for Higher Radix Modulo 2^n-1 Multiplication
Ramya Muralidharan, Chip Hong Chang, Singapore
17:00
A6-6 Area-saving Technique for Low-error Redundant Binary Fixed-width Multiplier Implementation
Tso-Bing Juang, Chip Hong Chang, Chi-Chung Wei, Taiwan
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Wednesday, 16 Dec 2009 |
B6 Special Session 4: Low-Power Circuits/Systems Design and Its Applications
Time: Wednesday, 16 Dec 2009, 15:30 – 17:20
Room: 309
Chairs: Yu-Cherng Hung |
15:30
B6-1 A Survey of Low-voltage Low-power Technique and Challenge for CMOS Signal Processing Circuits
Yu-Cherng Hung, Shao-Hui Shieh, Chiou-Kou Tung, Taiwan (Invited Paper)
15:48
B6-2 A Low Power Multi-voltage Control Technique with Fast-settling Mechanism for Low Dropout Regulator Jsung-Mo Shen, Wei-Bin Yang, Chang-Yu Hsieh, Yu-Lung Lo, Taiwan
16:06
B6-3 A Pseudo Fractional-N and Multiplier Clock Generator with 50% Duty Cycle Output using Low Power Phase
Combination Controller
Wan-Lun Gao, Wei-Bin Yang, Yu-Lung Lo, Taiwan
16:24
B6-4 An Efficiency Enhance Mixed-structure Charge Pump
Zong-Han Hsieh, Nan-Xiong Huang, Miin-Shyue Shiau, Hong-Chong Wu, Don-Gey Liu, Taiwan
16:42
B6-5 High Speed Laser Diode Driver
Heng Shou Hsu, Hung Chieh Chung, Taiwan
17:00
B6-6 A Novel Ultra-low Votage and Low Power OTA with Common-mode Feed-forward
Ming-Kai Fu, Miin-Shyue Shiau, Hong-Chong Wu, Don-Gey Liu, Taiwan
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Wednesday, 16 Dec 2009 |
C6 Special Session 7: High-speed and Low-complexity Implementation of Communication Systems
Time: Wednesday, 16 Dec 2009, 15:30 – 17:20
Room: 310
Chair: Younglok Kim |
15:30
C6-1 Performance Comparison of Various Post Processing Algorithms
Changtaek Shin, Jinyoung Lee, Jungjun Park, Younglok Kim, Korea (Invited Paper)
15:48
C6-2 High-speed Low-complexity Folded Degree-computationless Modified Euclidean Algorithm Architecture for
RS Decoders
Hyo-Jin Ahn, Chang-Seok Choi, Hanho Lee, Korea
16:06
C6-3 Linear Analysis and Speed Maximization of Feed Forward Ring Oscillators
Young-Seok Park, Pyung-Su Han, Woo-Young Choi, Korea
16:24
C6-4 1.25 Gb/s Burst-mode CMOS PON Laser Diode Driver with Automatic Power Controller
Young Joo Lee, Eun Chul Kang, Jinwook Burm, Korea
16:42
C6-5 Design of Remote Management System with ZigBee
Jeongsoo Park, Taewan Kim, Yunmo Chung, Korea
17:00
C6-6 Design of Wide-Bandwidth Sigma-Delta Modulator for Wireless Transceivers
Jungsu Choi, Kichang Jang, Junsang Lee, Wooju Jeong, Jungeui Park, Jayang Yoon, Seok Lee, Joongho Choi,
Korea
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Wednesday, 16 Dec 2009 |
D6 Special Session 13: Integrated Circuit Design from Tianjin University
Time: Wednesday, 16 Dec 2009, 15:30 – 17:20
Room: 311
Chairs: Suying Yao and Jianguo Ma |
15:30
D6-1 An Instruction Redundancy Removal Method on a Transport Triggered Architecture Processor
Su Wang, Suying Yao, Wei Guo, Zai-feng Shi, Jizeng Wei, China (Invited Paper)
15:48
D6-2 Analysis and Design of a High Performance Infrared Detector Readout Circuit
Yiqiang Zhao, Junwei Jiang, Fanzhong Meng, Ming Qu, Ming Wang, China
16:06
D6-3 A 330uW, 1.7GHz Locking Range LC Injection Locked Frequency Divider in CMOS Technology
Xuepo Ma, Wei Zhang, Xu Zhang, China
16:24
D6-4 Investigating the Effects of the Number of Stages on Phase Noise in CMOS Ring Oscillators
Weijie Zhu, Jianguo Ma, China
16:42
D6-5 A Metal-semiconductor-metal Photodetector in Si-based, Standard CMOS Technologies
Changliang Yu, Luhong Mao, Xindong Xiao, Shilin Zhang, Sheng Xie, China
17:00
D6-6 CdSe QDs-tagged-based Encoded Microparticle for Miniaturized and Multiplexed Immunoassay
Peng Gao, Suying Yao, Yuanqing Wu, Tao Luo, China
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Wednesday, 16 Dec 2009 |
E6 Design Automation: EMC/EMI
Time: Wednesday, 16 Dec 2009, 15:30 – 17:20
Room: 312
Chair: Kye Yak See |
15:30
E6-1 High-speed Signal Termination Analysis using a Co-simulation Approach
Weng-Yew Chang, Kye Yak See, Wei-Shan Soh, Manish Oswal, Lin-Biao Wang, Singapore
15:48
E6-2 Analysis of SMT Decoupling Capacitor Placement in Electronic Packages using Hybrid Modeling Method
Zaw Zaw Oo, En-Xiao Liu, Xingchang Wei, Yaojiang Zhang, Er-Ping Li, Singapore
16:06
E6-3 SI and EMI Performance of Signaling Scheme through UTP Cable
Lin-Biao Wang, Kye Yak See, Singapore
16:42
E6-4 System-level Conducted Electromagnetic Immunity Modelling Method
Eng-Kee Chua, Xian-Ke Gao, Er-Ping Li, Singapore
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Wednesday, 16 Dec 2009 |
P1 Device and IC Technology & Design Automation (Poster)
Time: Wednesday, 16 Dec 2009, 10:45 – 12:15
Venue: Level 3 Foyer
Chair: Cher Ming Tan |
P1-1 Computation of Charge Collection Probability For any Collecting Junction Shape
Oka Kurniawan, Vincent Keng Sian Ong, Chee Chin Tan, Singapore
P1-2 FPGA-based Built-in Testbed for Command Interpretations and Computational Load Distribution
Qi Cao, M. H. Lim, Singapore
P1-3 A Novel Gated Scan-cell Scheme for Low Capture Power (LCP) in At-speed Testing
Ming-Ying Chiang, Po-Han Wu, Jiann-Chyi Rau, Taiwan
P1-4 Obstacle-avoiding Electromigration Aware Wire Planning for Analog Circuits
Cheng-Chiang Lin, Hsin-Hsiung Huang, Hsi-An Chien, Tsai-Ming Hsieh, Taiwan
P1-5 Optimizing Multi-constraint VLSI Interconnect Routing
Zulkifli Md Yusof, Khalil-Hani, Muhammad Nadzir Marsono, N. Shaikh-Husin, Malaysia
P1-6 Temporal Partitioning Algorithm for a Coarse-grained Reconfigurable Computing Architecture
Chongyong Yin, Shoui Yin, Leibo Liu, Shaojun Wei, China
P1-7 New Look-up-table Optimizations for Memory-based Multiplication
Pramod Kumar Meher, Singapore
P1-8 A Robust Algorithm for DPA-resistant ECC
Yi Wang, China, L. Maskell Douglas, Singapore
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Wednesday, 16 Dec 2009 |
P2 Integrated Circuits & Integrated Systems (Poster)
Time: Wednesday, 16 Dec 2009, 13:30 – 15:00
Venue: Level 3 Foyer
Chair: Wang Ling Goh |
P2-1 Passive Circuit Designs toward Terahertz using Nanometer CMOS Technology
Kaixue Ma, Leyu Zhang, Kiat Seng Yeo, Singapore
P2-2 Implementation and Verification of Power Management Scheme over Indoor Multipath Channel at
UHF Bands
Wei Fu, Jianguo Ma, China
P2-3 CMP Service: BioMed Applications
Bernard Courtois, France
P2-4 A Low-complexity Ultra-low-power ECG Compression & Transmission Scheme
Hoe Yee Gan, Pradeep Gopalakrishnan, T. Hui Teo, Zhiming Chen, Singapore
P2-5 A Unified Signed-digit Adder for High-radix Modular Exponentiation on GF(p) and GF(2p)
Yi Wang, China, L. Maskell Douglas, Singapore
P2-6 Design of a Low-cost Airborne Radar Target Simulator based on FPGA
Li Lu, Xiancai Zhang, Jianming Lei, Xuecheng Zou, China
P2-7 A General Decoding Framework for High-rate LDPC Codes
Seyed Mohammad Ehsan Hosseini, Wang Ling Goh, Kheong Sann Chan, Singapore
P2-8 A Low Power Temperature Sensor for Passive RFID Tag
Yao Liu, Dong Seng Liu, Xuecheng Zou, Jian Bing Xu, Feng Bo Li, Shi Zhen Li, China
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