Special Session 3:
Circuits and System Architectures for Advanced Channel Coding
and Image Processing Applications
ORGANIZERS
Sau-Gee Chen, National Chiao Tung University, Taiwan and Pramod Kumar Meher, Institute for Infocomm Research, Singapore
SYNOPSIS
The explosive advancement of broadband communication since recent decade has been constantly posing enormous challenges for reliable data transmissions with increasingly high data rate. To answer the challenges, various advanced channel coding techniques have emerged and have been greatly improved recently, such as LDPC codes, turbo codes and etc.. Generally, as those advanced channel codecs process much longer code lengths and data rate than before, they often take up a big portion of the overall system resource, and become bottleneck of the system performances in practical realizations. Specifically, the current advanced channel codecs mostly have very high hardware complexities and high power consumption. Generally, hardware complexity is no longer an issue in the era of deep-submicron IC technology. However, power consumption is the most crucial problem in designing an environment-aware mobile device with extremely low-power consumption and long operating time.
With the mentioned technology challenges, this special session addresses the designs of future and current state-of-the-art high-performance, low-complexity and/or low-power channel codecs for various applications and efficient architectures for computer vision and image processing. The contributions of this special session include a new unconventional interpolation-based algorithm for hard-decision RS code and its decoder architectures, a multi-spec BCH decoder for DVB-S2, an LDPC decoding algorithm for 802.3c 10Gbps PHY system, CORDIC acceleration for Hough transform and other efficient hardware architectures for digital image processing applications.
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